Semiconductor storage

ABSTRACT

A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.

TECHNICAL FIELD

The present invention relates to an operation method of a semiconductorstorage device. More specifically, the present invention relates to asemiconductor storage device composed of a field-effect transistorhaving a function to convert changes of an electric charge amount to acurrent amount.

BACKGROUND ART

Conventionally, as a nonvolatile memory capable of storing two bits byone field-effect transistor, there has been a memory developed by SaifunSemiconductors Ltd. (refer to Kohyo (Japanese Unexamined PatentPublication) No. 2001-512290 for example). The structure of this priorart memory and the principle of its erase operation will be describedhereinbelow.

As shown in FIG. 22 of the present application, this memory is composedof a gate electrode 909 formed on a P type well region 901 through agate insulating film, and a first N type diffusion layer region 902 anda second N type diffusion layer region 903 formed on the surface of theP type well region 901. The gate insulating film is composed ofso-called ONO (Oxide Nitride Oxide) film in which a silicon nitride film906 is interposed between silicon oxide films 904 and 905. In thesilicon nitride film 906, there are formed memory holing portions 907,908 in the vicinity of the edge portions of the first and second N typediffusion layer regions 902, 903.

An amount of electric charges in each of these memory holing portions907, 908 is read as a drain current of a transistor so that two-bitinformation is stored in one transistor.

Next description will be given of an erase operation method in thismemory. The term “erase” is used herein to refer to the action ofreleasing electrons stored in the memory holing portions 907, 908. InKohyo (Japanese Unexamined Patent Publication) No. 2001-512290, therehas been disclosed a method for releasing electrons stored in a rightmemory holding portion 908 by applying 5.5V to the second diffusionlayer region 903 and −8V to the gate electrode 909, and extractingelectrons toward the drain electrode. This makes it possible to erasememory of a specific side among two memory holding portions. There hasbeen also disclosed a method for writing onto and reading from aspecific side. By combining these methods, two-bit operation is enabled.

However, in the above-stated memory, in order to provide the gateinsulating film with the function of operating the transistor as well asthe function as a memory film for storing electric charges, the gateinsulating film is formed into three-layer structure with use of ONOfilm. This makes it difficult to manufacture thinner gate insulatingfilms. Also, as the channel length is shortened, these two memory holingportions 907, 908 in one transistor interfere with each other, whichmakes two-bit operation difficult. This obstacles furtherminiaturization of the devices.

DISCLOSURE OF THE INVENTION

In view of the above problems, it is an object of the present inventionto provide a semiconductor storage device allowing furtherminiaturization while fulfilling two-bit memory holding in onetransistor.

In order to solve the above problems, a semiconductor storage device ina first aspect of the present invention comprises a first conductivitytype semiconductor substrate, a first conductivity type well regionprovided in a semiconductor substrate, or a first conductivity typesemiconductor film disposed on an insulator;

a gate insulating film formed on the first conductivity typesemiconductor substrate, the first conductivity type well regionprovided in the semiconductor substrate, or the first conductivity typesemiconductor film disposed on the insulator;

a single gate electrode formed on the gate insulating film;

two charge holding portions formed on sides of side walls of the singlegate electrode;

a channel region disposed under the single gate electrode; and

second conductivity type diffusion layer regions disposed on both sidesof the channel region, wherein

the charge holding portions are structured so as to change a currentamount flowing between one of the second conductivity type diffusionlayer regions and the other of the second conductivity type diffusionlayer regions when voltage is applied to the gate electrode by an amountof electric charges stored in the charge holding portions, wherein

a reference voltage is applied to the other of the second conductivitytype diffusion layer regions,

a first voltage is applied to the one of the second conductivity typediffusion layer regions, and

a second voltage is applied to the gate electrode such that carriers areinjected into the charge holding portion existing on the side of the oneof the second conductivity type diffusion layer regions.

According to the above structure, the two charge holding portions formedon the both sides of the side wall of the gate electrode are independentof the gate insulating film, so that the memory function implemented bythe charge holding portions and the transistor operation functionimplemented by the gate electrode are separated. Eventually, it is easyto make the gate insulating film thinner and control short channeleffect while maintaining sufficient memory function. Also, the twocharge holding portions formed on the both sides of the gate electrodeare separated by the gate electrode, which enables effective restraintof interference in rewrite operation. In other words, a distance betweenthese two charge holding portions may be shortened.

Further, by appropriately setting the voltage of the gate electrode, thevoltage of the one of the second conductivity type diffusion layerregions, and the voltage of the other of the second conductivity typediffusion layer regions, it becomes possible to selectively injectingcarriers to the charge holding portion on the side of the one of thesecond conductivity type diffusion layer regions. This makes it possibleto provide a semiconductor storage device enabling two-bit operation andfacilitating miniaturization.

Herein, when the first conductivity type is P type, the secondconductivity type is N type, and the carriers are positive holes.Contrary to this, when the first conductivity type is N type, the secondconductivity type is P type, and the carriers are electrons. Also, whenthe first voltage is higher than the reference voltage, the secondvoltage is lower than the reference voltage. When the first voltage islower than the reference voltage, the second voltage is higher than thereference voltage.

In one embodiment, a third voltage is applied to the first conductivitytype semiconductor substrate, the first conductivity type well regionprovided in the semiconductor substrate, or the first conductivity typesemiconductor film disposed on the insulator.

According to the semiconductor storage device in the present embodiment,forward-direction voltage is applied to a PN junction between the otherof the second conductivity type diffusion layer regions, and, the firstconductivity type semiconductor substrate, the first conductivity typewell region provided in the semiconductor substrate, or the firstconductivity type semiconductor film disposed on the insulator. As aresult, either ones of electrons and positive holes are injected intothe semiconductor substrate. The injected electrons or positive holesare accelerated and diffused in the PN junction between the other of thesecond conductivity type diffusion layer regions, and, the firstconductivity type semiconductor substrate, the first conductivity typewell region provided in the semiconductor substrate, or the firstconductivity type semiconductor film disposed on the insulator, as aresult of which pairs of an electron and a positive hole are generated.The others among thus-generated electrons or positive holes areselectively injected as carriers into the charge holding portionexisting on the side of the other of the second conductivity typediffusion layer regions. This process also occurs in the case wherevoltage difference between the other of the second conductivity typediffusion layer regions and the semiconductor substrate is relativelylow, which makes it possible to lower the operating voltage of thesemiconductor storage device. Therefore, it becomes possible to achievelower consumption power and the control of device deterioration of thesemiconductor storage device.

In one embodiment, the first conductivity type is P type,

the second conductivity type is N type,

the carriers are positive holes,

the first voltage is higher than the reference voltage, and

the second voltage is lower than the reference voltage, and

the third voltage is higher than the reference voltage.

According to the above embodiment, the voltage of the one of the N typediffusion layer regions is set higher than the reference voltage, andthe voltage of the gate electrode is set lower than the referencevoltage so as to enable selective injection of positive holes into thecharge holding portion on the side of the one of the N type diffusionlayer regions.

Also, the voltage of the P type semiconductor substrate, the P type wellregion provided in the semiconductor substrate, or the P typesemiconductor film disposed on the insulator is set higher than thereference voltage, so that forward-direction voltage is applied to thePN junction between the P type semiconductor substrate, the P type wellregion provided in the semiconductor substrate, or the P typesemiconductor film disposed on the insulator, and, the other of the Ntype diffusion layer regions, by which electrons are injected into thesemiconductor substrate. The injected electrons are accelerated anddiffused in the PN junction between the one of the N type diffusionlayer regions, and, the P type semiconductor substrate, the P type wellregion provided in the semiconductor substrate, or the P typesemiconductor film disposed on the insulator, as a result of which pairsof an electron and a positive hole are generated. The positive holesamong these are selectively injected into the charge holding portionexisting on the side of the one of the N type diffusion layer regions.This process also occurs in the case where voltage difference betweenthe other of the N type diffusion layer regions and the semiconductorsubstrate is relatively low, which makes it possible to lower theoperating voltage of the semiconductor storage device. Therefore, itbecomes possible to achieve lower consumption power and the control ofdevice deterioration of the semiconductor storage device.

In one embodiment, the first conductivity type is N type,

the second conductivity type is P type,

the carriers are electrons,

the first voltage is lower than the reference voltage, and

the second voltage is higher than the reference voltage, and

the third voltage is lower than the reference voltage.

According to the above embodiment, the voltage of the one of the P typediffusion layer regions is set lower than the reference voltage, and thevoltage of the gate electrode is set higher than the reference voltageso as to enable selective injection of electrons into the charge holdingportion existing on the side of the one of the P type diffusion layerregions.

Also, the voltage of the N type semiconductor substrate, the N type wellregion provided in the semiconductor substrate, or the N typesemiconductor film disposed on the insulator is set lower than thereference voltage, so that forward-direction voltage is applied to thePN junction between the N type semiconductor substrate, the N type wellregion provided in the semiconductor substrate, or the N typesemiconductor film disposed on the insulator, and, the other of the Ptype diffusion layer regions, by which positive holes are injected intothe semiconductor substrate. The injected positive holes are acceleratedand diffused in the PN junction between the one of the P type diffusionlayer regions, and, the N type semiconductor substrate, the N type wellregion provided in the semiconductor substrate, or the N typesemiconductor film disposed on the insulator, as a result of which pairsof an electron and a positive hole are generated. The electrons amongthese are selectively injected into the charge holding portion existingon the side of the one of the P type diffusion layer regions. Thisprocess also occurs in the case where voltage difference between theother of the P type diffusion layer regions and the semiconductorsubstrate is relatively low, which makes it possible to lower theoperating voltage of the semiconductor storage device. Therefore, itbecomes possible to achieve lower consumption power and the control ofdevice deterioration of the semiconductor storage device.

In one embodiment, the second conductivity type diffusion layer regionshave an offset structure without an overlap region overlapping the gateelectrode with interposition of the gate insulating film.

According to the above embodiment, the semiconductor storage device hasso-called offset transistor structure, which makes it possible to obtainlarge memory effect. Since the semiconductor storage device has theoffset structure, due to potential of the gate electrode, an effect ofpromoting generation of either ones of positive holes or electrons isreduced in the PN junction between the one of the second conductivitytype diffusion layer regions and the first conductivity typesemiconductor substrate or the like. Contrary to this, to the PNjunction between the other of the second conductivity type diffusionlayer regions and the first conductivity type semiconductor substrate orthe like, forward-direction voltage is applied. Eventually withrelatively low voltage, in the PN junction between the one of the secondconductivity type diffusion layer regions and the first conductivitytype semiconductor substrate or the like, the others among positiveholes and electrons are generated as carriers to be injected into thecharge holding portion existing on the side of the one of the secondconductivity type diffusion layer regions. Therefore, it becomespossible to provide a semiconductor storage device having large memoryeffect and enabling low voltage operation.

In one embodiment, an absolute value of voltage difference between thesecond voltage and third voltage is 0.7V or more and 1V or less.

According to the above embodiment, there may be obtained forward-currentflowing to the PN junction between the other of the second conductivitytype diffusion layer regions, and, the first conductivity typesemiconductor substrate, the first conductivity type well regionprovided in the semiconductor substrate, or the first conductivity typesemiconductor film disposed on the insulator, that is enough forgenerating positive holes or electrons as carriers in the PN junctionbetween the one of the second conductivity type diffusion layer regions,and, the first conductivity type semiconductor substrate, the firstconductivity type well region provided in the semiconductor substrate,or the first conductivity type semiconductor film disposed on theinsulator. Also, the forward-direction current will not causeconsiderable increase of current consumption in the semiconductorstorage device.

Also, in one embodiment, a gate length of the gate electrode is 0.015 μmor more and 0.5 μm or less.

According to the above embodiment, in the PN junction between the one ofthe second conductivity type diffusion layer regions and the firstconductivity type semiconductor substrate or the like, positive holesand electrons are sufficiently generated, which makes it possible toinject them into the charge holding portion. Also, transistor operation,that is the basics of memory operation, may be secured.

Also in one embodiment, the charge holding portion is composed of afirst insulator, a second insulator, and a third insulator,

the charge holding portion has a structure in which a film composed ofthe first insulator having a function of storing electric charges isinterposed between the second insulator and the third insulator,

the first insulator is silicon nitride, and

the second and third insulators are silicon oxide.

According to the above embodiment, the first insulator having a functionof storing the electric charges is silicon nitride, in which a number oflevels for trapping electric charges (electrons and positive holes) arepresent, so that large hysteresis property may be obtained. Also, sincethe second and third insulators are silicon oxide, the charge holdingportion has so-called NON (Oxide Nitride Oxide) film structure, whichincrease injection efficiency of electric charges and enables high-speedrewrite operation.

Also in one embodiment, a thickness of the film composed of the secondinsulator on the channel region is smaller than a thickness of the gateinsulating film and is 0.8 nm or more.

According to the above embodiment, the thickness of the film composed ofthe second insulator that separates the film composed of the firstinsulator having a function of storing electric charges from the channelregion is smaller than the thickness of the gate insulating film and is0.8 nm or more, which enables decrease of voltage for write operationand erase operation or enables high-speed write operation and eraseoperation without degrading withstanding voltage capability of thememory, thereby enabling increase of memory effect.

Also in one embodiment, a thickness of the film composed of the secondinsulator on the channel region is larger than a thickness of the gateinsulating film and is 20 nm or less.

According to the above embodiment, the thickness of the film composed ofthe second insulator that separates the film composed of the firstinsulator having a function of storing electric charges from the channelregion is larger than the thickness of the gate insulating film and is20 nm or less, which enables improvement of holding characteristicswithout worsening short channel effect of the memory.

Also in one embodiment, the film composed of the first insulator havinga function of storing electric charges includes a portion having asurface that is approximately parallel to a surface of the gateinsulating film.

According to the above embodiment, it becomes possible to increase arewrite speed while preventing deterioration of electric charge holdingcharacteristics of the semiconductor storage device.

Also in one embodiment, the film composed of the first insulator havinga function of storing electric charges includes a portion extending indirection approximately parallel to a lateral side of the gateelectrode.

According to the above embodiment, the film composed of the firstinsulator having a function of storing electric charges includes aportion extending in direction approximately parallel to a lateral sideof the gate electrode so that an electric charge amount injected intothe film composed of the first insulator having a function of storingelectric charges in rewrite operation is increased and high-speed writeoperation is enabled.

Also in one embodiment, at least part of the charge holding portion isformed so as to overlap part of the second conductivity type diffusionlayer region.

According to the above embodiment, it becomes possible to increase readcurrent of the semiconductor storage device and to restrain dispersionof the read current, thereby enabling high-speed read operation of thesemiconductor storage device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an outlined cross sectional view showing main part of a firstexample of the semiconductor storage device in a first embodiment of thepresent invention;

FIG. 2 is an outlined cross sectional view showing main part of a secondexample of the semiconductor storage device in the first embodiment ofthe present invention;

FIG. 3 is an outlined cross sectional view showing main part of a thirdexample of the semiconductor storage device in the first embodiment ofthe present invention;

FIGS. 4A and 4B are outlined cross sectional views showing main part ofthe semiconductor storage device of the present invention for describingwrite operation thereof;

FIG. 5 is an outlined cross sectional view showing main part of thesemiconductor storage device of the present invention for describingfirst erase operation thereof;

FIG. 6 is an outlined cross sectional view showing main part of thesemiconductor storage device of the present invention for describingsecond erase operation thereof;

FIGS. 7A and 7B are energy diagrams against electrons in cross sectionalline A–A′ of FIG. 6;

FIG. 8 is a graph showing change of erase capability along with changeof gate length in the second erase method of the semiconductor storagedevice of the present invention;

FIG. 9 is an outlined cross sectional view showing main part of thesemiconductor storage device in a second embodiment of the presentinvention;

FIG. 10 is an outlined cross sectional view showing enlarged main partof the semiconductor storage device of FIG. 9;

FIG. 11 is an outlined cross sectional view showing enlarged main partof a modified example of the semiconductor storage device of FIG. 9;

FIG. 12 is a graph showing electric characteristics of the semiconductorstorage device in the second embodiment of the present invention;

FIG. 13 is an outlined cross sectional view showing main part of amodified example of the semiconductor storage device in the secondembodiment of the present invention;

FIG. 14 is an outlined cross sectional view showing main part of thesemiconductor storage device in a third embodiment of the presentinvention;

FIG. 15 is an outlined cross sectional view showing main part of thesemiconductor storage device in a fourth embodiment of the presentinvention;

FIG. 16 is an outlined cross sectional view showing main part of thesemiconductor storage device in a fifth embodiment of the presentinvention;

FIG. 17 is an outlined cross sectional view showing main part of thesemiconductor storage device in a sixth embodiment of the presentinvention;

FIG. 18 is an outlined cross sectional view showing main part of thesemiconductor storage device in a seventh embodiment of the presentinvention;

FIG. 19 is an outlined cross sectional view showing main part of thesemiconductor storage device in an eighth embodiment of the presentinvention;

FIG. 20 is a graph showing electric characteristics of the semiconductorstorage device in a ninth embodiment of the present invention;

FIG. 21 is a graph showing electric characteristics of a conventionalflash memory; and

FIG. 22 is an outlined cross sectional view showing main part of aconventional semiconductor storage device.

BEST MODE FOR CARRYING OUT THE INVENTION

A semiconductor storage device of the present invention is mainlycomposed of a gate insulating film, a gate electrode formed on the gateinsulating film, a charge holding portion formed on the both sides ofthe gate electrode, source/drain regions (diffusion layer regions)disposed separately on the side of the charge holding portion opposed tothe gate electrode, and a channel region disposed under the gateelectrode.

The semiconductor storage device functions as a memory device storingfour-valued or more information by storing binary or more information inone charge holding portion. However, the semiconductor storage devicefunctions not necessarily to store four-valued or more information, butit may also functions to store, for example, binary information.

It is preferable that the semiconductor storage device of the presentinvention is formed on a semiconductor substrate, preferably on a firstconductivity type well region formed in the semiconductor substrate.

Examples of the semiconductor substrate are not particularly limited andinclude those for use in semiconductor apparatuses, such as substratesmade from elemental semiconductors including silicon and germanium,substrates made from compound semiconductors including GaAs, InGaAs andZnSc, various substrates including SOI substrates and multilayer SOIsubstrates, and substrates having a semiconductor layer on a glass andplastic substrate. Among these, a silicon substrate or SOI substratehaving a silicon layer formed as a surface semiconductor layer ispreferable. The semiconductor substrate or the semiconductor layer maybe either single crystal (e.g., single crystal obtained by epitaxialgrowth), multi-crystal, or amorphous, though a current amount flowinginside will change.

On the semiconductor substrate or the semiconductor layer, it ispreferable that a device isolation region is formed, and it is morepreferable to combine a device such as transistors, capacitors andresists, a circuit composed thereof, a semiconductor device, and aninter-layer insulating film to form a single or a multilayer structure.It is noted that the device isolation region may be formed with variousdevice isolation films including LOCOS films, trench oxide films, andSTI films. The semiconductor substrate may have either P type or N typeconductivity type, and it is preferable that at least one firstconductivity type (P type or N type) well region is formed on thesemiconductor substrate. Acceptable impurity concentration of thesemiconductor substrate and the well region is those within the knownrange in the art. It is noted that in the case of using SOI substrate asthe semiconductor substrate, a well region may be formed in the surfacesemiconductor layer, and also a body region may be provided under thechannel region.

Examples of the gate insulating film are not particularly limited andinclude those for use in typical semiconductor apparatuses, such as:insulating films including silicon oxide films and silicon nitridefilms; and high-dielectric films including aluminum oxide films,titanium oxide films, tantalum oxide films, hafnium oxide films, in theform of single-layer films or multi-layer films. Among these, thesilicon oxide film is preferable. An appropriate thickness of the gateinsulating film is, for example, approx. 1 to 20 nm, preferably 1 to 6nm. The gate insulating film may be only formed right under the gateelectrode, and may be formed to be larger (in width) than the gateelectrode.

The gate electrode is formed on the gate insulating film in the formtypically used in semiconductor apparatuses. Unless particularlyspecified in the embodiment, examples of the gate electrode are notparticularly limited and therefore include such conductive films as:polysilicon; metals including copper and aluminum; high-melting metalsincluding tungsten, titanium, and tantalum; and high-melting metals andsilicide in the form of a single-layer or a multi-layer. An appropriatefilm thickness of the gate electrode is approx. 50 to 400 nm. It isnoted that under the gate electrode, a channel region is formed, thoughthe channel region is preferably formed not only under the gateelectrode but also under the region including the gate electrode and theoutside of the gate edge in longitudinal direction of the gate. Thus, inthe case where there is present a channel region which is not coveredwith the gate electrode, the channel region is preferably covered withthe gate insulating film or a later-described charge holding portion.

The charge holding portion at least includes a film or a region having afunction of holding electric charges or storing and holding electriccharges, or a function of trapping electric charges. Articlesimplementing these functions include: silicon nitride; silicon; silicateglass including impurities such as phosphorus and boron; siliconcarbide; alumina; high-dielectric substances such as hafnium oxide,zirconium oxide, tantalum oxide; zinc oxide; and metals. The chargeholding portion may be formed into single-layer or multi-layer structurewith: for example, an insulating film containing a silicon oxide film;an insulating film containing a conductive film or a semiconductor layerinside; and an insulating film containing one or more semiconductors orsemiconductor dots. Among these, the silicon oxide is preferable becauseit may achieve large hysteresis property by the presence of a number oflevels for trapping electric charges, and has good holdingcharacteristics since long electric-charge holding time preventselectric charges from leaking due to generation of leakage pas, andfurther because it is a material normally used in LSI process.

Use of an insulating film containing inside an insulating film having acharge holding function such as silicon nitride films enables increaseof reliability relating to memory holding. Since the silicon nitridefilm is an insulator, electric charges of the entire silicon nitridefilm will not be immediately lost even if part of the electric chargesis leaked. Further, in the case of arraying a plurality of memorydevices (semiconductor storage devices), even if the distance betweenthe memory devices is shortened and adjacent charge holding portionscome into contact with each other, information stored in each chargeholding portion is not lost unlike the case where the charge holdingportion is made from a conductor. Also, it becomes possible to dispose acontact plug closer to the charge holding portion, or in some cases itbecomes possible to dispose the contact plug so as to overlap with thecharge holding portion, which facilitates miniaturization of the memorydevices.

For further increase of the reliability relating to the memory holding,an insulating film having a function of holding electric charges is notnecessarily in the film shape, and an insulator having the function ofholding an electric charge is preferably present in the insulating filmin a discrete manner. More specifically, it is preferable that aninsulator is dispersed like dots over a material having difficulty inholding electric charges, such as silicon oxide.

Also, use of an insulator film containing inside a conductive film or aconductor layer as a charge holding portion enables free control ofquantity of electric charges injected into the conductor or thesemiconductor, thereby bringing about an effect of facilitatingachieving multi level cell.

Further, using an insulator film containing one or more conductors orsemiconductor dots as a charge holding portion facilitates execution ofwrite and erase due to direct tunneling of electric charges, therebybringing about an effect of reduced power consumption.

More specifically, it is preferable that the charge holding portionfurther contains a film having a region that obstructs escape ofelectric charges or a function of obstructing escape of electriccharges. Those fulfilling the function of obstructing escape of electriccharges include a silicon oxide.

The charge holding portion is formed on the both sides of the gateelectrode directly or through an insulating film, and it is directlydisposed on a semiconductor substrate (a well region, a body region, ora source/drain region or a diffusion layer region) through the gateinsulating film or the insulating film. A charge holding film on theboth sides of the gate electrode may be formed so as to cover the entireside walls of the gate electrode directly or thought he insulating film,or it may be formed so as to cover part thereof. In the case of using aconductive film as the charge holding film, the charge holding film ispreferably disposed through an insulating film so that the chargeholding film is not brought into direct contact with a semiconductorsubstrate (a well region, a body region, or a source/drain region or adiffusion layer region) or the gate electrode. This is implemented by,for example, a multi-layer structure composed of a conductive film andan insulating film, a structure of dispersing a conductive film likedots in an insulating film, and a structure of disposing a conductivefilm within part of a side-wall insulating film formed on the side wallof the gate.

The charge holding portion preferably has a sandwich structure in whicha film made of a first insulator for storing electric charges isinterposed in between a film made of a second insulator and a film madeof a third insulator. Since the first insulator for storing electriccharges is in the film shape, it becomes possible to increase electriccharge concentration in the first insulator in a short period of time byinjection of electric charges and also to uniform the electric chargeconcentration. In the case where the electric charge distribution in thefirst insulator for storing electric charges is not uniform, there is apossibility that electric charges move inside the first insulator duringbeing held and so the reliability of the memory devices is deteriorated.Also, the first insulator for storing electric charges is separated froma conductor portion (a gate electrode, a diffusion layer region, and asemiconductor substrate) with other insulating film, which may restrainleakage of electric charges and makes it possible to obtain sufficientholding time. Therefore, the above sandwich structure enables high-speedrewrite operation, increased reliability, and obtainment of sufficientholding time of the semiconductor storage device. The charge holdingportion that fulfils the above conditions is more preferably structuredsuch that the first insulator is to be a silicon nitride film, and thesecond and the third insulators are to be silicon oxide films. Thesilicon nitride film may achieve large hysteresis property by thepresence of a number of levels for trapping electric charges. Also, thesilicon oxide film as well as the silicon nitride film are preferablebecause they are materials used in LSI process quite normally. Further,as the first insulator, in addition to silicon nitride, there may beused such materials as hafnium oxide, tantalum oxide, and yttrium oxide.As the second and third insulators, in addition to the silicon oxide,such material as aluminum oxide may be used. It is noted that the secondand third insulators may be different materials or may be the samematerial.

The charge holding portion is formed on the both sides of the gateelectrode, and disposed on a semiconductor substrate (a well region, abody region, or a source/drain region or a diffusion layer region).

The charge holding film contained in the charge holding portion isformed on the both sides of the gate electrode directly or through aninsulating film, and it is directly disposed on a semiconductorsubstrate (a well region, a body region, or a source/drain region or adiffusion layer region) through the gate insulating film or theinsulating film. A charge holding film on the both sides of the gateelectrode is preferably formed so as to cover all or part of side wallsof the gate electrode directly or thought the insulating film. In thecase where the gate electrode has a recess portion on the lower edgeside as an application example, the charge holding film may be formed soas to fill the entire recess portion or part of the recess portiondirectly or through the insulating film.

Preferably, the gate electrode is formed only on the side wall of thecharge holding portion or formed such that the upper portion of thecharge holding portion is not covered. In such disposition, it becomespossible to dispose a contact plug closer to the gate electrode, whichfacilitates miniaturization of the memory devices. Also, the memorydevices having such simple disposition are easily manufactured,resulting in an increased yield.

The source/drain region is separately disposed on the side of the chargeholding portion opposed to the gate electrode as a diffusion layerregion having a conductivity type opposite to that of a semiconductorsubstrate or a well region. In the portion where the source/drain regionis joined to the semiconductor substrate or the well region, impurityconcentration is preferably sharp. This is because the sharp impurityconcentration efficiently generate hot electrons and hot positive holeswith low voltages, which enables high-speed operation with lowervoltages. The junction depth of the source/drain region is notparticularly limited and so it is adjustable where necessarycorresponding to performance and the like of a semiconductor storagedevice to be manufactured. It is noted that if SOI substrate is used asa semiconductor substrate, the junction depth of the source/drain regionmay be smaller than the film thickness of a surface semiconductor layer,though preferably the junction depth is almost equal to the filmthickness of the surface semiconductor layer.

The source/drain region may be disposed so as to be overlapped with theedge of the gate electrode, or may be disposed so as to be offset fromthe edge of the gate electrode. Particularly, it is preferable that thesource/drain region is offset from the edge of the gate electrode. Thisis because in this case, when voltage is applied to the gate electrode,easiness of inversion of the offset region under the charge holding filmis largely changed by an electric charge amount stored in the chargeholding portion, resulting in increased memory effect and reduced shortchannel effect. It is noted, however, that too much offset extremelyreduces drive current between the source and the drain. Therefore, it ispreferable that an offset amount, that is a distance from one edge ofthe gate electrode to the source or drain region closer thereto in thelongitudinal direction of the gate, is shorter than the thickness of thecharge holding film parallel to the longitudinal direction of the gate.What is particularly important is that at least part of the electriccharge storage region in the charge holding portion overlaps with partof the source/drain region as a diffusion layer region. This is becausethe nature of memory devices constituting the semiconductor storagedevices of the present invention is to rewrite memory with an electricfield crossing the charge holding portion by voltage difference betweenthe gate electrode present only on the side wall portion of the chargeholding portion and the source/drain region.

Part of the source/drain region may be extensively provided in theposition higher than the surface of the channel region, that is, thelower face of the gate insulating film. In this case, it is appropriatethat a conductive film integrated with the source/drain region islaminated on the source/drain region formed in the semiconductorsubstrate. Examples of the conductive film include semiconductors suchas polysilicon and amorphous silicon, silicide, the above describedmetals, and high-melting metals. Among these, the polysilicon ispreferable. Since the polysilicon is extremely larger in impuritydiffusion speed than the semiconductor substrate, it is easy to shallowthe junction depth of the source/drain region in the semiconductorsubstrate, and it is easy to control short channel effect. In this case,it is preferable that the source/drain region is disposed such that atleast part of the charge holding film is interposed in between part ofthe source/drain region and the gate electrode.

The semiconductor storage device of the present invention uses a singlegate electrode formed on the gate insulating film, a source region, adrain region, and a semiconductor substrate as four terminals, andexecutes write, erase and read operations by giving specified potentialto each of these four terminals. An example of specific operationprinciple and operation voltage will be described later. When thesemiconductor storage devices of the present invention are disposed inan array to constitute a memory cell array, a single control gate iscapable of control each memory cell, which makes it possible to decreasethe number of word lines.

The semiconductor storage device of the present invention may be formedin a normal semiconductor process by a method similar to, for example, amethod for forming a multilayer-structured side wall spacer on the sidewall of a gate electrode. More specifically, there is a method in whichafter the gate electrode is formed, a multilayer composed of aninsulating film (second insulator), an electric charge storage film(first insulator), and an insulating film (second insulator) is formedand etched back under an appropriate condition to leave the film in theform of a side wall spacer. In addition, corresponding to the structureof a desired charge holding portion, conditions and deposits in formingthe side wall may be appropriately selected.

The semiconductor storage device of the present invention is applicableto portable electronic apparatuses and more particularly to portableinformation terminals. Examples of the portable electronic apparatusesinclude portable information terminals, cell phones, and gaming devices.

Hereinbelow, a semiconductor storage device of the present inventionwill be described in detail with reference to drawings.

(First Embodiment)

The structure of a memory device constituting a semiconductor storagedevice of the present embodiment will be described with reference toFIGS. 1 to 3. FIGS. 1 to 3 are outlined cross sectional views showingmemory devices whose structure of a charge holding portion in the shapeof side wall spacer is different from each other.

The memory device constituting the semiconductor storage device of thepresent embodiment is formed as a nonvolatile memory cell capable ofstoring two bits, in which, as shown in FIGS. 1 to 3, a gate electrode13 having a gate length similar to normal transistors is formed on asemiconductor substrate 11 through a gate insulating film 12, and chargeholding portions 61, 62 in the shape of side wall spacer are formed onthe side walls of the gate insulating film 12 and the gate electrode 13.On the side of the charge holding portions 61, 62 facing the gateelectrode 13, there are formed a first diffusion layer region 17 and asecond diffusion layer region 18 (source/drain regions). Thesource/drain regions 17, 18 are offset from the edge portion of the gateelectrode 13 (from a region 41 where the gate electrode 13 is formed).

Thus, the charge holding portions of the memory transistor are formedindependently of the gate insulating film. Consequently, a memoryfunction implemented by the charge holding portions and a transistoroperation function implemented by the gate insulating film areseparated. Since two charge holding portions formed on the both sides ofthe gate electrode are separated by the gate electrode, interference inrewrite operation is effectively controlled. Therefore, the memorytransistor is capable of storing two bits information and enables easyminiaturization.

Further, since the source/drain regions 17, 18 are offset from the gateelectrode 13, easiness of inversion of an offset region 42 under thecharge holding film is largely changed by an electric charge amountstored in the charge holding portion when voltage is applied to the gateelectrode, which enables increase of memory effect. Further, compared tonormal logic transistors, short channel effect may be stronglyprevented, which enables further miniaturization of the gate length.Also, since the memory transistor is structurally suitable forcontrolling the short channel effect, it becomes possible to adopt agate insulating film with a large film thickness compared to logictransistors, thereby enabling increase of reliability.

The charge holding portion in the shape of side wall spacer may becomposed of, as shown in FIG. 1 for example, a silicon nitride film 21in the shape of side wall and a silicon oxide film 14 for separating thesilicon nitride film 21 from the gate electrode 13, the semiconductorsubstrate 11, and the source/drain regions 17, 18. It is the siliconnitride film 21 that has a function of storing electric charges(electrons or positive holes), and the silicon oxide film 14 preventsthe electric charges stored in the silicon nitride film 21 from leaking.

As shown in FIG. 2, another example of the charge holding portion iscomposed of a conductive film 22 in the shape of side wall and a siliconoxide film 14 for separating the conductive film 22 from the gateelectrode 13, the semiconductor substrate 11, and the source/drainregions 17, 18. It is the conductive film 22 that has a function ofstoring electric charges, and the silicon oxide film 14 prevents theelectric charges stored in the conductive film 22 from leaking.

The charge holding portion may further has a structure shown in FIG. 3.The charge holding portion in the shape of side wall spacer has astructure in which a silicon nitride film 15 is interposed in betweensilicon oxide films 14, 16. The silicon nitride film 15 has a functionof trapping and storing electric charges (electrons or positive holes).Storing of electric charges is mainly implemented by a portion presenton the offset region 42. Since the charge holding portion has astructure in which the silicon nitride film 15 is interposed in betweenthe silicon oxide films 14, 16 as shown above, efficiency of injectingelectric charges into the charge holding portion is increased andhigh-speed rewrite operation (write and erase operation) is enabled.

The structure of the charge holding portion is not limited to the abovethree examples (FIGS. 1 to 3), and therefore such structure ascontaining quantum dots having a function of storing electric charges inthe charge holding portion is also acceptable. Also, the charge holdingportion does not need to have a side wall shape, as long as the chargeholding portion is in the both sides of the gate electrode and partthereof is in contact with the semiconductor substrate 11 and thesource/drain regions 17, 18.

Next, the operation principle of the memory device will be describedwith reference to FIGS. 4 to 8. It is noted that although FIGS. 4 to 6show memory devices having the charge holding portion shown in FIG. 3,the operation principle is applicable to memory devices having chargeholding portions in other shapes.

First, description will be given of write operation of the memory devicewith reference to FIG. 4. It is noted that the term “write” refers tothe action of injecting electrons into the charge holding portion whenthe memory device is N channel type, and to the action of injectingpositive holes into the charge holding portion when the memory device isP channel type. When the memory device is N channel type, the firstconductivity type semiconductor substrate 11 is P type and secondconductivity type diffusion layer regions 17, 18 are N type. When thememory device is P channel type, conductivity type of each component isreversed. In the following description (including description about readmethod an erase method), there is shown the case where the memory deviceis N channel type. As for the case of P channel type, reversing thefunction of electrons and positive holes will do. Also in the case of Pchannel type, all the marks of voltages to be applied to each node maybe reversed. The write operation of the memory is executed by injectinghot electrons accelerated by drain electric fields into the chargeholding portion.

In order to inject electrons (write) into a second charge holdingportion 62, as shown in FIG. 4A, a first diffusion layer region 17 isset to be a source electrode and a second diffusion layer region 18 isset to be a drain electrode. For example, there may be applied 0V to thefirst diffusion layer region 17 and the semiconductor substrate 11, +5Vto the second diffusion layer region 18, and +4V to a gate electrode 13.Under these voltage conditions, an inversion layer 31 extends from thediffusion layer region 17 (source electrode) but fails to reach thesecond diffusion layer region 18 (drain electrode), resulting ingenerating a pinchoff point. Electrons are accelerated by high electricfields from the pinchoff point to the second diffusion layer region 18(drain electrode) and turn to be so-called hot electrons (high energyconductive electrons). By injecting these hot electrons into the secondcharge holding portion 62 (more precisely the silicon nitride film 15),write operation is executed. It is noted that in the vicinity of a firstcharge holding portion 61, hot electrons are not generated and thereforewrite operation is not executed. Thus, electrons are injected to thesecond charge holding portion 62 so as to enable write operation.

In order to inject electrons (write) into the first charge holdingportion 61, as shown in FIG. 4B, the second diffusion layer region 18 isset to be a source electrode, and the first diffusion layer region 17 isset to be a drain electrode. For example, there may be applied 0V to thesecond diffusion layer region 18 and the semiconductor substrate 11, +5Vto the first diffusion layer region 17, and +4V to the gate electrode13. Thus, by reversing the source and drain regions in the case ofinjecting electrons into the second charge holding portion 62, electronsare injected into the first charge holding portion 61 for enabling writeoperation.

Next, description will be given of the principle of read operation ofthe memory device (unshown).

In the case of reading information stored in the first charge holdingportion 61, the first diffusion layer region 17 is set to be a sourceelectrode and the second diffusion layer region 18 is set to be a drainelectrode, and a transistor is operated in the saturated region. Forexample, there may be applied 0V to the first diffusion layer region 17and the semiconductor substrate 11, +2V to the second diffusion layerregion 18, and +1 to the gate electrode 13. Herein, if no electron isstored in the first charge holding portion 61, drain current tends toflow. In the case where electrons are stored in the first charge holdingportion 61, an inversion layer is hardly formed in the vicinity of thefirst charge holding portion 61, and so the drain current does not tendto flow. Therefore, detecting the drain current makes it possible toread information stored in the first charge holding portion 61. Here,whether or not electric charges are stored in the second charge holdingportion 62 does not affect the drain current since the vicinity of thedrain is pinched off.

In the case of reading information stored in the second charge holdingportion 62, the second diffusion layer region 18 is set to be a sourceelectrode, and the first diffusion layer region 17 is set to be a drainelectrode, and a transistor is operated in the saturated region. Forexample, there may be applied 0V to the second diffusion layer region 18and the semiconductor substrate 11, +2V to the first diffusion layerregion 17, and +1V is applied to the gate electrode 13. Thus, byreversing the source and drain regions in the case of readinginformation stored in the first charge holding portion 61, informationstored in the second charge holding portion 62 may be read.

It is noted that if a channel region (offset region 41, 42) not coveredwith the gate electrode 13 is remained, the presence of excessiveelectrons in the charge holding portions 61, 62 eliminates or forms theinversion layer in the channel region not covered with the gateelectrode 13, as a result of which large hysteresis (change ofthreshold) may be obtained. However, if the width of the offset region42 is too large, the drain current is drastically reduced, therebycausing considerable delay of a read speed. Therefore, it is preferableto determine the width of the offset region 42 so as to enableobtainment of sufficient hysteresis and read speed.

In the case where the diffusion layer regions 17, 18 reach the edge ofthe gate electrode 13, that is, if the diffusion layer regions 17, 18and the gate electrode 13 are overlapped, write operation causes almostno change to a threshold of the transistor, though parasitic resistanceat the edge of the source/drain regions suffers considerable change,resulting in remarkable reduction of the drain current (one digit ormore). Therefore, detection of the drain current enables read operationand provides a function as a memory. However, if larger memoryhysteresis effect is required, it is preferable that the diffusion layerregions 17, 18 and the gate electrode 13 are not overlapped (that theoffset region 42 is present).

Next, description will be given of a first erase method of thesemiconductor storage device with reference to FIG. 5.

In the case of erasing information stored in the second charge holdingportion 62, a positive voltage (e.g., +5V) is applied to the seconddiffusion layer region 18 as the one of the second conductivity typediffusion layer regions, while at the same time, 0V is applied to thesemiconductor substrate 11, so that reverse bias is imparted to the PNjunction between the second diffusion layer region 18 and thesemiconductor substrate 11. Further, a negative voltage (e.g., −5V) isapplied to the gate electrode 13. Here, in the vicinity of the gateelectrode 13 among the PN junction area, potential gradient becomesparticularly steep because of the influence of the gate electrode towhich a negative voltage is applied. Consequently, positive holes aregenerated on the side of the semiconductor substrate 11 in the PNjunction area due to interband tunneling. The positive holes are pulledtoward the gate electrode 13 having negative potential, as a result ofwhich positive holes are injected into the second charge holding portion62. Thus, erase operation of the second charge holding portion 62 isperformed. In this point, 0V may be applied to the first diffusion layerregion 17 as the other of the second conductivity type diffusion layerregions, or the first diffusion layer region 17 may be put into openstate.

In the above erase method, for erasing information stored in the firstcharge holding portion 61, potential of the first diffusion layer regionand the second diffusion layer region may be reversed.

Next, description will be given of a second erase method of thesemiconductor storage device with reference to FIGS. 6 and 7.

In the case of erasing information stored in the second charge holdingportion 62, as shown in FIG. 6, there may be applied a positive voltage(e.g., +4V) to the second diffusion layer region 18 as the one of thesecond conductivity type diffusion layer regions, 0V to the firstdiffusion layer region 17 as the other of the second conductivity typediffusion layer regions, a negative voltage (e.g., −4V) to the gateelectrode 13, and a positive voltage (e.g., +0.8V) to the semiconductorsubstrate 11. More particularly, with the voltage of the other of the Ntype diffusion layer regions (first diffusion layer region 17) beingused as a reference voltage, the voltage of the one of the N typediffusion layer regions (second diffusion layer region 18) is set higherthan the reference voltage, the voltage of the gate electrode 13 is setlower than the reference voltage, and the voltage of a semiconductorsubstrate of P type as a first conductivity type (semiconductorsubstrate 11) is set higher than the reference voltage. It is noted thatvoltages applied to each node are relative. Consequently, if the voltageof the semiconductor substrate 11 is a reference voltage (0V), the abovecondition is equivalent to the condition in which the voltage of thesecond diffusion layer region 18 is +3.2V, the voltage of the firstdiffusion layer region 17 is −0.8V, and the voltage of the gateelectrode 13 is −4.8V. In other words, the voltage of the firstconductivity type semiconductor substrate (P type semiconductorsubstrate 11) is set to be a reference voltage, the voltage of the otherof the second conductivity type regions (first N type diffusion layerregion 17) is set lower than the reference voltage, the voltage of theone of the second conductivity type diffusion layer regions (second Ntype diffusion layer region 18) is set higher than the referencevoltage, and the voltage of the gate electrode 13 is set lower than thereference voltage.

In the case of disposing the semiconductor storage devices of thepresent embodiment in a cell array, it is preferable to use a P typesemiconductor storage device common to each memory device (morespecifically, a memory cell array is formed on one semiconductorsubstrate, or a common P type well region is formed in a semiconductorsubstrate and a memory cell array is formed thereon), and to fixpotential of the P type semiconductor substrate in operating thesemiconductor storage devices. This is because since the common P typesemiconductor substrate has a PN junction whose area is extremely large,fluctuating the potential of the P type semiconductor substrategenerates large current flow in filling the capacity of this PNjunction.

FIGS. 7A and 7B show energy diagrams (energy band diagrams) againstelectrons in cross sectional line A–A′ of FIG. 6. FIG. 7A shows theenergy band when 0V that is the same voltage as the first diffusionlayer region 17 is applied to the semiconductor substrate 11 (potentialof other nodes is similar to that of FIG. 6), while FIG. 7B shows theenergy band when +0.8V is applied to the semiconductor substrate 11(that is the same condition as that shown in FIG. 6). In FIGS. 7A and7B, Ec represents a conduction electron band edge and Ev representsvalence band edge. A gap between Ec and Ev shows a band gap.

In the case of FIG. 7A, though absolute values of voltages aredifferent, the energy band is essentially the same as that in the firsterase method. In this case, between the semiconductor substrate 11 andthe second diffusion layer region 18, there should be given potentialdifferent enough for causing interband tunneling. The second erasemethod is for generating positive holes and executing erase operationeven if potential difference between the semiconductor substrate 11 andthe second diffusion layer region 18 is not enough for causing interbandtunneling. The most important point in the second erase method is toapply forward-direction voltage to the PN junction between the firstdiffusion layer region 17 and the semiconductor substrate 11. As shownin FIG. 7B, if the forward-direction voltage is applied, potential ofthe semiconductor substrate 11 is declined from a dotted line to a solidline. Eventually, electrons are injected from the first diffusion layerregion 17 to the semiconductor substrate 11 (electron 51). The electron51 injected to the semiconductor substrate reaches the PN junctionbetween the second diffusion layer region 18 and the semiconductorsubstrate 11, where the electron 51 is accelerated by electric fieldsand loses energy by diffusion (electron 52). The energy lost at thispoint is received by valence band electrons, resulting in generation ofpairs of an electron 53 and a positive hole 54. Thus, in the PN junctionbetween the second diffusion layer region 18 and the semiconductorsubstrate 11, positive holes are generated, and they are furtherinjected into the second charge holding portion 62, by which eraseoperation works.

According to the second erase method, it becomes possible to generatepositive holes and to perform erase operation even if backward-directionbias applied to the second diffusion layer region 18 and thesemiconductor substrate 11 is relatively small. This makes it possibleto lower operating voltage of memory devices. Therefore, it becomespossible to fulfill reduced power consumption and restraineddeterioration of memory devices. Particularly when the offset region 42is present, the effect that the gate electrode to which negativepotential is applied makes potential of the PN junction steep becomessmall. This makes generation of positive holes by interband tunnelingdifficult. The second erase method covers this defect and fulfils eraseoperation with low voltage. Therefore, in the memory device of thepresent invention in which providing the offset region 42 increasesmemory effect, the second erase method is particularly preferable.

When forward-direction bias applied to between the first diffusion layerregion 17 and the semiconductor substrate 11 is 0.7V or more, eraseoperation is performed, whereas the forward-direction bias is less than0.7V, erase operation is not performed at all. When theforward-direction bias exceeds 1V, forward-direction current increasesand therefore current consumed in erase operation shows considerableincrease. Therefore, the forward-direction bias is preferably 0.7V ormore and 1V or less.

In the above second erase method, for erasing information stored in thefirst charge holding portion 61, potential of the first diffusion layerregion and potential of the second diffusion layer region may bereversed.

FIG. 8 is a view showing change of erase capability along with change ofthe gate length in the second erase method. In an experiment forcreating FIG. 8, a threshold value of a memory device was measured afterwrite operation was conducted onto the memory device, and then anthreshold value was re-measured after erase operation by the seconderase method was conducted. An initial threshold value before conductingwrite operation was approx. 0.4V. After write operation was conducted,the threshold value incremented to almost the same level (0.85V)regardless of the gate length. It was found out that after eraseoperation was conducted, the threshold value was lowered to almost thesame level (0.4V) when the gate length was 0.5 μm or less, but the erasecapability was rapidly decreased along with increase of the gate lengthwhen the gate length was 0.6 μm or more. Such phenomenon may beattributed to the following. In FIG. 7B, the electron 51 injected fromthe first diffusion layer region 17 into the semiconductor substrate 11can reach the PN junction between the second diffusion layer region 18and the semiconductor substrate 11 when the gate length (channel length)is sufficiently short. However, when the gate length (channel length) islong, the electron 51 is lost due to recombination or receives repulsionfrom the gate electrode having negative potential, which considerablyreduces the number of the electrons 51 before the electron 51 reachesthe PN junction. Thus, the characteristics as shown in FIG. 8 areconsidered to be obtained. Based on this finding, the gate length of thememory device is preferably 0.5 μm or less. As described before, thismemory device is particularly suitable for miniaturization. However,with the gate length being 0.015 μm or less, transistor operation itselfbecomes difficult. In view of these, it is preferable that the gatelength of the memory device is 0.015 μm or more and 0.5 my or less.

Although in the above operation method, two-bit write and eraseoperation per transistor is achieved by reversing the source electrodeand the drain electrode, it is also possible to fix the source electrodeand the drain electrode to operate the memory device as one-bit memory.In this case, it becomes possible to set the voltage of either one ofthe source and drain regions to be a common fixed voltage, which enablesreduction of the number of bit lines connected to the source/drainregion.

It is understood that the above operation method is applicable not onlyto the semiconductor storage device of the present embodiment but alsoto the semiconductor storage devices of other embodiments.

According to the semiconductor storage device of the present embodiment,the charge holding portion of the memory transistor is formed on theboth sides of the gate electrode independently of the gate insulatingfilm. This makes it possible to execute two-bit operation. Further,since each of the charge holding portion is separated by the gateelectrode, interruption in rewrite operation is effectively controlled.Also, the memory function implemented by the charge holding portion andthe transistor operation function implemented by the gate insulatingfilm are separated, decreasing the thickness of the gate insulating filmenables restraint of short channel effect. Consequently, it becomespossible to miniaturize the device.

Also, according to the second erase method of the semiconductor storagedevice, it becomes possible to generate positive holes with relativelylow voltage and to execute erase operation. This makes it possible toreduce operating voltage of the memory device. Consequently, reducedpower consumption and controlled deterioration of the memory device maybe fulfilled. Further, in the memory device of the present inventionwhose memory effect is increased by offsetting the diffusion layerregion from the gate electrode, the second erase method has particularlylarge effect of decreasing erase operation voltage.

(Second Embodiment)

In a semiconductor storage device in this embodiment as shown in FIG. 9,charge holding portions 161, 162 are composed of a region for holdingelectric charges (the region for storing electric charges, which may bea film having a function of holding electric charges) and a region forobstructing release of electric charges (which may be a film having afunction of obstructing release of electric charges). The semiconductorstorage device has, for example, ONO structure. More specifically, thecharge holding portions 161, 162 are structured in the state that a film142 as a first insulator made of silicon nitride being interposed inbetween a film 141 as a second insulator made of a silicon oxide and afilm 143 as a third insulator made of silicon oxide. Here, the siliconnitride film 142 implements a function of storing and holding electriccharges. The silicon oxide films 141, 143 implement a function ofobstructing release of the electric charges stored in the siliconnitride film.

Also, the region (silicon nitride film 142) for holding electric chargesin the charge holding portions 161, 162 are overlapped with thediffusion layer regions 112, 113. Herein, the term “overlap” is used torefer to the state that at least part of the region (silicon nitridefilm 142) for holding electric charges is present on at least part ofthe diffusion layer regions 112, 113. It is noted that there are shown asemiconductor substrate 111, a gate insulating film 114, a gateelectrode 117, and an offset region 171 (between the gate electrode andthe diffusion layer region). Though unshown in the drawing, theuppermost surface of the semiconductor substrate 111 under the gateinsulating film 114 is a channel region.

Description will be given of an effect of overlapping the region 142 forholding electric charges in the charge holding portions 161, 162 and thediffusion layer regions 112, 113.

FIG. 10 is an enlarged view showing the vicinity of the charge holdingportion 162 that is on the right side of FIG. 9. Reference numeral W1denotes an offset amount between the gate insulating film 114 and thediffusion layer region 113. Also, reference numeral W2 denotes the widthof the charge holding portion 162 on the cross sectional plane inchannel length direction of the gate electrode. Since an edge of thesilicon nitride film 142 on the side away from the gate electrode 117 inthe charge holding portion 162 is aligned with an edge of the chargeholding portion 162 on the side away from the gate electrode 117, thewidth of the charge holding portion 162 is defined as W2. An overlapamount between the charge holding portion 162 and the diffusion layerregion 113 is represented by an equation W2−W1. What is particularlyimportant is that the silicon nitride film 142 in the charge holdingportion 162 is overlapped with the diffusion layer region 113, that is,the relation of W2>W1 is satisfied.

In the case where an edge of a silicon nitride film 142 a on the sideaway from the gate electrode in a charge holding portion 162 a is notaligned with an edge of the charge holding portion 162 a on the sideaway from the gate electrode as shown in FIG. 11, W2 may be defined asthe width from the edge of the gate electrode to the edge of the siliconnitride film 142 a on the side away from the gate electrode.

FIG. 12 shows a drain current Id in the structure of FIG. 10 with thewidth W2 of the charge holding portion 162 being fixed to 100 nm and theoffset amount W1 being varied. Herein, the drain current is obtained bydevice simulation performed under the conditions that the charge holdingportion 162 is in erase state (positive holes are stored), and thediffusion layer regions 112, 113 are set to be a source electrode and adrain electrode, respectively.

As shown in FIG. 12, with W1 being 100 nm or more (i.e., when thesilicon nitride film 142 and the diffusion layer region 113 are notoverlapped), the drain current shows rapid reduction. Since a draincurrent value is almost in proportion to a read operation speed, memoryperformance is rapidly deteriorated when W1 is 100 nm or more. In therange where the silicon nitride film 142 and the diffusion layer region113 are overlapped, the drain current shows mild reduction. Therefore,it is preferable that at least part of the silicon nitride film 142 thatis a film having a function of holing electric charges is overlappedwith the source/drain region.

Based on the above-described result of the device simulation, a memorycell array is manufactured with W2 being fixed to 100 nm, and W1 beingset to 60 nm and 100 nm as design values. When W1 is 60 nm, the siliconnitride film 142 is overlapped with the diffusion layer regions 112, 113by 40 nm as a design value, and when W1 is 100 nm, there is no overlapas a design value. As a result of measuring read time of these memorycell arrays in comparison with the worst cases in consideration todispersion, it was found out that the case where W1 was 60 nm as adesign value was 100 times faster in readout access time. From apractical standpoint, it is preferable that the read access time is 100nanoseconds or less per bit. It was found out, however, that thiscondition was never satisfied in the case of W1=W2. It was also foundout that W2−W1>10 nm was more preferable in consideration tomanufacturing dispersion.

In the semiconductor storage device in FIG. 9 to FIG. 11, it ispreferable for reading information stored in the charge holding portion161 (region 181) to set the diffusion layer region 112 as a sourceelectrode and the diffusion layer region 113 as a drain region similarto the embodiment 1 and to form a pinchoff point on the side closer tothe drain region in the channel region. More specifically, in readinginformation stored in either one of two charge holding portions, thepinchoff point is preferably formed in a region closer to the othercharge holding portion in the channel region. This makes it possible todetect memory information in the charge holding portion 161 with goodsensitivity regardless of the storage condition of the charge holdingportion 162, resulting in large contribution to implementation oftwo-bit operation.

In the case of storing information only in one side out of the twocharge holding portions 161, 162, or in the case of using these twocharge holding portions 161, 162 in the same storing condition, anpinchoff point is not necessarily formed in read operation.

Although not shown in FIG. 9, a well region (P type well in the case ofN-channel device) is preferably formed on the surface of thesemiconductor substrate 111. Forming the well region facilitates controlof other electric characteristics (withstand voltage, junctioncapacitance, and short channel effect) while maintaining impurityconcentration of the channel region optimum for memory operation(rewrite operation and read operation).

From the viewpoint of improving memory holding characteristic, thecharge holding portion preferably contains a charge holding film havinga function of holing electric charges and an insulating film. In thisembodiment, there are used a silicon nitride film 142 as a chargeholding film having levels for trapping electric charges, and siliconoxide films 141, 143 as insulating films having a function of preventingthe electric charges stored in the charge holding film from dispersing.The charge holding portion containing the charge holding film and theinsulating film makes it possible to prevent electric charges fromdispersing and to improve holding characteristic. Further, compared tothe charge holding portion composed of only a charge holding film, itbecomes possible to appropriately decrease the volume of the chargeholding film. Appropriate decrease of the volume of the charge holdingfilm makes it possible to restrain movement of electric charges in thecharge holding film and to control occurrence of characteristic changedue to movement of electric charges during memory holding.

Also, it is preferable that the charge holding portion contains a chargeholding film disposed approximately parallel to the surface of the gateinsulating film. In other words, it is preferable that the surface ofthe charge holding film in the charge holding portion is disposed so asto have a constant distance from the surface of the gate insulatingfilm. More particularly, as shown in FIG. 13, a charge holding film 142a in the charge holding portion 162 has a face approximately parallel tothe surface of the gate insulating film 114. In other words, the chargeholding film 142 a is preferably formed to have a uniform height fromthe height corresponding to the surface of the gate insulating film 114.The presence of the charge holding film 142 a approximately parallel tothe surface of the gate insulating film 114 in the charge holdingportion 162 makes it possible to effectively control easiness offormation of an inversion layer in the offset region 171 with use of anamount of electric charges stored in the charge holding film 142 a,thereby enabling increase of memory effect. Also, by placing the chargeholding film 142 a approximately parallel to the surface of the gateinsulating film 114, change of memory effect may be kept relativelysmall even with a dispersed offset amount (W1), enabling restraint ofmemory effect dispersion. In addition, movement of electric chargestoward upper side of the charge holding film 142 a may be controlled,and therefore characteristic change due to the movement of electriccharges during memory holding may be restrained.

Furthermore, the charge holding portion 162 preferably contains aninsulating film (e.g., a portion of the silicon oxide film 144 on theoffset region 171) that separates the charge holding film 142 aapproximately parallel to the surface of the gate insulating film 114from the channel region (or the well region). This insulating film mayrestrain dispersion of the electric charges stored in the charge holdingfilm, thereby contributing to obtaining a semiconductor storage devicewith better holding characteristics.

It is noted that controlling the film thickness of the charge holdingfilm 142 a as well as controlling the film thickness of the insulatingfilm under the charge holding film 142 a (a portion of the silicon oxidefilm 144 on the offset region 171) to be constant make it possible tokeep the distance from the surface of the semiconductor substrate to theelectric charges stored in the charge holding film approximatelyconstant. More particularly, the distance from the surface of thesemiconductor substrate to the electric charges stored in the chargeholding film may be controlled to be within the range from a minimumfilm thickness value of the insulating film under the charge holdingfilm 142 a to the sum of a maximum film thickness of the insulating filmunder the charge holding film 142 a and a maximum film thickness of thecharge holding film 142 a. Consequently, the concentration of electricline of force generated by the electric charges stored in the chargeholding film 142 a may be roughly controlled, and therefore dispersionof the degree of memory effect of the memory device may be minimized.

(Third Embodiment)

In this embodiment, a charge holding film 142 as a film made of a firstinsulator in the charge holding portion 162 has an approximately uniformfilm thickness as shown in FIG. 14. Further, the charge holding film 142includes a first portion 181 as a portion having the surfaceapproximately parallel to the surface of the gate insulating film 114and a second portion 182 as a portion extending in directionapproximately parallel to the side face of the gate electrode 117.

When a positive voltage is applied to the gate electrode 117, electricline of force in the charge holding portion 162 passes the siliconnitride film 142 total two times through the first portion 181 and thesecond portion 182 as shown with an arrow 183. It is noted that when anegative voltage is applied to the gate electrode 117, the direction ofelectric line of force is reversed. Herein, a dielectric constant of thesilicon nitride film 142 is approx. 6, while a dielectric constant ofsilicon oxide films 141, 143 is approx. 4. Eventually, an effectivedielectric constant of the charge holding portion 162 in the directionof electric line of force 183 becomes larger than that in the case wherethe charge holding film 142 includes only the first portion 181, whichmakes it possible to decrease potential difference between the bothedges of the electric line of force. More specifically, much part of thevoltage applied to the gate electrode 117 is used to reinforce electricfields in the offset region 171.

Electric charges are injected into the silicon nitride film 142 inrewrite operation because generated electric charges are pulled byelectric fields in the offset region 171. As a consequence, the chargeholding film 142 including the second portion 182 increases the electriccharges injected into the charge holding portion 162 in rewriteoperation, thereby increasing a rewrite speed.

In the case where the portion of the silicon oxide film 143 is a siliconnitride film, more specifically, in the case where the charge holdingfilm is not constant against the height corresponding to the surface ofthe gate insulating film 114, movement of electric charges toward upperside of the silicon nitride film becomes outstanding, and holdingcharacteristics are deteriorated.

Instead of silicon oxide film, the charge holding portion is morepreferably formed from high-dielectric substances such as hafnium oxidehaving extremely large dielectric constant.

Further, the charge holding portion more preferably includes aninsulating film (a portion of the s141 on the offset region 171) thatseparates the charge holding film approximately parallel to the surfaceof the gate insulating film from the channel region (or the wellregion). This insulating film may restrain dispersion of the electriccharges stored in the charge holding film, thereby enabling furtherimprovement of holding characteristics.

Also, the charge holding portion more preferably includes an insulatingfilm (a portion of the silicon oxide film 141 in contact with the gateelectrode 117) that separates the gate electrode from the charge holdingfilm extending in the direction approximately parallel to the side faceof the gate electrode. This insulating film may prevent injection ofelectric charges from the gate electrode into the charge holding filmand prevent change of electric characteristics, which may increasereliability of the semiconductor storage device.

Further, similar to the second embodiment, it is preferable that thefilm thickness of the insulating film under the charge holding film 142(a portion of the silicon oxide film 141 on the offset region 171) iscontrolled to be constant, and further the film thickness of theinsulating film disposed on the side face of the gate electrode (aportion of the silicon oxide film 141 in contact with the gate electrode117) is controlled to be constant. Consequently, the concentration ofelectric line of force generated by the electric charges stored in thecharge holding film 142 may be roughly controlled, and leakage ofelectric charges may be prevented.

(Fourth Embodiment)

This embodiment relates to optimization of the distance between a gateelectrode, a charge holding portion, and a source/drain region.

As shown in FIG. 15, reference symbol A denotes a gate electrode lengthin the cross section in channel length direction, reference symbol Bdenotes a distance (channel length) between source and drain regions,and reference symbol C denotes a distance from the edge of one chargeholding portion 161 to the edge of the other charge holding portion 162,more specifically a distance from the edge of a film 142 (the side awayfrom the gate electrode 117) having a function of holding the electriccharges in one charge holding portion 161 in the cross section inchannel length direction to the edge of a film 142 (the side away fromthe gate electrode 117) having a function of holding the electriccharges in the other charge holding portion 162.

First, an equation B<C is preferable. In the channel region, there ispresent an offset region 171 between a portion under the gate electrode117 and the source/drain regions 112, 113. Since B<C, the electriccharges stored in the charge holding portions 161, 162 (silicon nitridefilm 142) effectively fluctuate easiness of inversion in the entire partof the offset region 171. As a result, memory effect is increased, andhigh-speed read operation is particularly enabled.

Also, when the gate electrode 117 and the source/drain regions 112, 113are offset, that is when an equation A<B is satisfied, easiness ofinversion of the offset region when a voltage is applied to the gateelectrode 117 is largely changed by an electric charge amount stored inthe charge holding portions 161, 162. Consequently, memory effectincreases and short channel effect can be reduced. However, as long asthe memory effect is effective, the offset region is not necessarilyrequired. Even when the offset region 171 is not present, if theimpurity concentration in the source/drain regions 112, 113 issufficiently small, the memory effect can still be effective in thecharge holding portions 161, 162 (silicon nitride film 142). Therefore,the state of A<B<C is most preferable.

(Fifth Embodiment)

A semiconductor storage device in this embodiment has essentially thesame structure as that in the second embodiment except that thesemiconductor substrate is SOI substrate as shown in FIG. 16.

The semiconductor storage device is structured such that an embeddedoxide film 188 is formed on a semiconductor substrate 186, and on top ofthe embedded oxide film 188, SOI layer is further formed. In the SOIlayer, there are formed diffusion layer regions 112, 113, and otherareas constitute a body region 187.

This semiconductor storage device also brings about the working effectssimilar to those of the semiconductor storage device in the thirdembodiment. Further, since the junction capacitance between thediffusion layer regions 112, 113 and the body region 187 may beconsiderably reduced, it becomes possible to increase a device speed andto decrease power consumption.

(Sixth Embodiment)

A semiconductor storage device in this embodiment has essentially thesame structure as that in the second embodiment except that in thevicinity of the channel side of N type source/drain regions 112, 113, aP type highly-concentrated region 191 is added as shown in FIG. 17.

More specifically, the concentration of P type impurity (e.g., boron) inthe P type highly-concentrated region 191 is higher than theconcentration of P type impurity in the region 192. An appropriate valueof the P type impurity concentration in the P type highly-concentratedregion 191 is, for example, around 5×10¹⁷ to 1×10¹⁹ cm⁻³. Also, a valueof the P type impurity concentration in the region 192 may be set to,for example, 5×10¹⁶ to 1×10¹⁸ cm⁻³.

Thus, providing the P type highly-concentrated region 191 makes thejunction between the diffusion layer regions 112, 113 and thesemiconductor substrate 111 steep right under the charge holdingportions 161, 162. This facilitates generation of hot carriers in writeand erase operation, thereby enabling reduction of voltage in writeoperation and erase operation or implementing high-speed write operationand erase operation. Further, since the impurity concentration in theregion 192 is relatively small, a threshold value when the memory is inerased state is small and so the drain current becomes large.Consequently, a read speed is increased. This makes it possible toprovide a semiconductor storage device having low rewrite voltage or ahigh rewrite speed, and having a high read speed.

Also in FIG. 17, by providing the P type highly-concentrated region 191in a position adjacent to the source/drain region and on the lower sideof the charge holding portions 161, 162 (that is a position not rightunder the gate electrode), a threshold value of the entire transistorshows considerable increase. The degree of this increase is extremelylarger than that in the case where the P type highly-concentrated region191 is right under the gate electrode 117. When write electric charges(electrons in the case where the transistor is N channel type) arestored in the charge holding portions 161, 162, the difference becomeslarger. When enough erase electric charges (positive holes in the casewhere the transistor is N channel type) are stored in the charge holdingportion, a threshold value of the entire transistor is decreased down toa value determined by the impurity concentration in the channel region(region 192) under the gate electrode 117. More specifically, thethreshold value in the erased state is not dependent on the impurityconcentration in the P type highly-concentrated region 191, whereas thethreshold value in the written state receives extremely large influence.Therefore, disposing the P type highly-concentrated region 191 that isunder the charge holding portions 161, 162 and adjacent to thesource/drain region imparts extremely large fluctuation only to thethreshold value in the written state, thereby enabling remarkableincrease of memory effect (difference of threshold values in the erasedstate and the written state).

(Seventh Embodiment)

A semiconductor storage device in this embodiment has essentially thesame structure as that in the second embodiment except that thethickness T1 of the insulating film 141 that separates the chargeholding portion (silicon nitride film 142) from the channel region orthe well region is smaller than the thickness T2 of the gate insulatingfilm 114 as shown in FIG. 18.

The gate insulating film 114 has a lower limit of the thickness T2because of the request for withstand voltage in memory rewriteoperation. However, the thickness T1 of the insulating film 141 thatseparates the charge holding portion (silicon nitride film 142) from thechannel region or the well region can be smaller than T2 regardless ofthe request for withstand voltage.

In the semiconductor storage device in the present embodiment, thethickness T1 of the insulating film has high design freedom as statedabove because of the following reason. In the semiconductor storagedevice in the present embodiment, the insulating film 141 that separatesthe charge holding film 142 from the channel region or the well regionis not interposed in between the gate electrode 117 and the channelregion or the well region. Consequently, the insulating film 141 thatseparates the charge holding film 142 from the channel region or thewell region does not receive direct influence from the high-electricfields that affect in between the gate electrode 117 and the channelregion or the well region, but receives influence from relatively weakelectric fields expanding from the gate electrode 117 in horizontaldirection. As a result, despite the request for withstand voltage to thegate insulating film 114, it becomes possible to make T1 smaller thanT2. Contrary to this, for example in EEPROM as typified by flash memory,an insulating film that separates a floating gate from the channelregion or the well region is interposed in between a gate electrode(control gate) and the channel region or the well region, so that theinsulating film receives direct influence from high electric fields ofthe gate electrode. In EEPROM, therefore, the thickness of theinsulating film that separates the floating gate from the channel regionor the well region is limited, which hinders optimization of thefunctions of a memory device. As is clear from the above, an essentialreason of high freedom of T1 is the fact that the insulating film 141that separates the charge holding film 142 from the channel region orthe well region in the memory device of the present embodiment is notinterposed in between the gate electrode 117 and the channel region orthe well region.

Decreasing the thickness T1 of the insulating film facilitates injectionof electric charges into the charge holding portions 161, 162, decreasesvoltage for write operation and erase operation, or enables high-speedwrite operation and erase operation. In addition, since an electriccharge amount induced in the channel region or the well regionincrements when electric charges are stored in the silicon nitride film142, increased memory effect may be implemented.

Some electric lines of force in the charge holding portion do not passthe silicon nitride film 142 as shown with an arrow 184 in FIG. 14.Since electric field strength is relatively large on such a shortelectric line of force, the electric fields along the electric line offorce plays an important role in rewrite operation. By decreasing thethickness T1 of the insulating film 141, the silicon nitride film 142moves to the lower side of the FIG. 14, so that the electric line offorce shown with the arrow 184 passes the silicon nitride film 142. As aconsequence, an effective dielectric constant in the charge holdingportion along the electric line of force 184 becomes large, which makesit possible to make potential difference between the both ends of theelectric line of force 184 smaller. Therefore, most part of voltageapplied to the gate electrode 117 is used to strengthen the electricfields in the offset region, thereby implementing high-speed writeoperation and erase operation.

As is clear from the above, the thickness T1 of the insulating film 141that separates the silicon nitride film 142 from the channel region orthe well region and the thickness T2 of the gate insulating film 114 aredefined as T1<T2 so as to decrease voltage in write operation and eraseoperation or implement high-speed write operation and erase operation,and to enable further increase of memory effect without degradingwithstand voltage capability of the memory.

It is noted that the thickness T1 of the insulating film is preferably0.8 nm or more, that is the limit range in which uniformity inmanufacturing process or certain level of film quality may be maintainedand holding characteristics do not suffer extreme deterioration.

More specifically, in the case of liquid crystal driver LSI which has asevere design rule and requires high withstand voltage, maximum 15 to18V voltage is necessary for driving liquid crystal panel TFT.Eventually, it is not possible to make the gate oxide film thinner. Inthe case of mounting a nonvolatile memory of the present invention as animage adjuster together with other devices on the liquid crystal driverLSI, the memory device of the present invention enables optimum designof the thickness of an insulating film that separates the charge holdingfilm (silicon nitride film 242) from the channel region or the wellregion independently of the gate insulating film. For example, in amemory cell with a gate electrode length (word line width) of 250 nm,there may be separately set like T1=20 nm and T2=10 nm, fulfilling amemory cell with good write efficiency. (Short channel effect is notgenerated even though T1 is larger than that of normal logictransistors, because the source/drain region is offset from the gateelectrode.)

(Eighth Embodiment)

A semiconductor storage device in this embodiment has essentially thesame structure as that in the second embodiment except that thethickness T1 of the insulating film 141 that separates the chargeholding film (silicon nitride film 142) from the channel region or thewell region is larger than the thickness T2 of the gate insulating film114 as shown in FIG. 19.

The gate insulating film 114 has an upper limit of the thickness T2because of the request for prevention of short channel effect of thedevice. However, the thickness T1 of the insulating film 141 on thelower side of the charge holding film 142 can be larger than T2regardless of the request for prevention of short channel effect. Morespecifically, as miniaturization scaling proceeds (the gate insulatingfilm 114 becomes smaller), the thickness of the insulating film 141 thatseparates the charge holding film (silicon nitride film 142) from thechannel region or the well region may be optimally designedindependently of the thickness T2 of the gate insulating film, whichimplements the effect that the charge holding portion will not disturbscaling.

In the semiconductor storage device of the present embodiment, thethickness T1 of the insulating film 141 has high design freedom asstated above because, as is already described, the insulating film 141that separates the charge holding film 142 from the channel region orthe well region is not interposed in between the gate electrode 117 andthe channel region or the well region. As a result, despite the requestfor prevention of short channel effect to the gate insulating film 114,it becomes possible to make T1 larger than T2.

Increasing the thickness of the insulating film 141 makes it possible toprevent dispersion of the electric charges stored in the charge holdingfilm 142 and to improve holing characteristics of the memory.

Therefore, setting as T1>T2 enables improvement of holdingcharacteristics without deteriorating short channel effect of thememory.

It is noted that the thickness T1 of the insulating film 141 ispreferably 20 nm or less in consideration of reduction of a rewritespeed.

More specifically, a conventional nonvolatile memory as typified byflash memory is structured such that a selection gate electrodeconstitutes a write/erase gate electrode, and a gate insulating film(including a floating gate) corresponding to the write/erase gateelectrode serves also as an electric charge storage film. Consequently,since the request for miniaturization (creation of thinner devices isessential for restraining short channel effect) conflicts the requestfor securing reliability (in order to control leakage of stored electriccharges, the thickness of an insulating film that separates a floatinggate from the channel region or the well region cannot be decreased tosmaller than approx. 7 nm), miniaturization of the device is difficult.In fact, according to ITRS (International Technology Roadmap forSemiconductors), miniaturization of a physical gate length down toapprox. 0.2 micron or lower is not yet in sight. In the semiconductorstorage device of the present invention, independent designing of T1 andT2 is available as described above, and therefore miniaturizationbecomes possible. In the present invention, for example, in a memorycell with a gate electrode length (word line width) of 450 nm, there isseparately set like T2=4 nm and T1=7 nm, fulfilling a semiconductorstorage device free from generation of short channel effect. Shortchannel effect is not generated even though T2 is set larger than thatof normal logic transistors, because the source/drain region is offsetfrom the gate electrode. Also, since the source/drain region is offsetfrom the gate electrode in the semiconductor storage device of thepresent invention, miniaturization is further facilitated compared tonormal logic transistors.

As described above, according to the semiconductor storage device of thepresent invention, since an electrode for supporting write and eraseoperation is not present above the charge holding portion, theinsulating film that separates the charge holding film from the channelregion or the well region does not directly receive the influence ofhigh electric fields that affect in between the electrode that supportswrite and erase operation and the channel region or the well region, butreceives influence only from relatively weak electric fields expandingfrom the gate electrode in horizontal direction. This makes it possibleto fulfill a memory cell having the gate length miniaturized more thanthe gate length of the logic transistors in comparison with the sameprocessing generations.

(Ninth Embodiment)

This embodiment relates to changes of electric characteristics whenrewrite operation is performed in the semiconductor storage device ofthe present invention.

FIG. 20 is a view showing changes of a drain current Id(A) against agate voltage Vg(V) in the erased state and written state where anelectric charge amount in the charge holding portion of an N-channeltype memory device is different, with curve lines, wherein a horizontalaxis expresses the gate voltage Vg(V) and a vertical axis expresses thedrain current ID(A). As clearly shown in FIG. 20, when write operationis performed in the erased state (solid line), not only the thresholdvalue simply rises, but inclination of the graph dramatically fallsespecially in sub-threshold region. Therefore, even in the region withrelatively high gate voltage (Vg), a drain current ratio of the erasedstate to the written state is large. For example in the point ofVg=2.5V, the current ratio is still two digits or more. Thischaracteristic is largely different from that in the case of a flashmemory shown in FIG. 21. FIG. 21 is a view, similar to FIG. 20, showingchanges of a drain current Id(A) against a gate voltage Vg(V) in theerased state and written state in a flash memory, with curved lines.

The emergence of the above characteristic in the semiconductor storagedevice of the present embodiment is a phenomenon peculiar to the casewhere the gate electrode and the diffusion region are offset andtherefore the gate electric fields are difficult to reach the offsetregion. When the semiconductor storage device is in the written state,an inversion layer is extremely difficult to be generated in the offsetregion below the charge holding portion even if a positive voltage isapplied to the gate electrode. This causes smaller inclination of theId-Vg curve line in the sub-threshold region in the written state. Whenthe semiconductor storage device is in the erased state, high-densityelectrons are induced in the offset region. Further, when 0V is appliedto the gate electrode (i.e., in OFF state), electrons are not induced inthe channel below the gate electrode (because of which an off current issmall). This causes large inclination of the Id-Vg curve line in thesub-threshold region in the erased state and a large increase rate(conductance) even in the region over the threshold.

As is clear from the above description, the semiconductor storage deviceof the present invention makes it possible to make the drain currentratio of the erased state to the written state particularly large.

1. A semiconductor storage device comprising: a first conductivity typesemiconductor substrate, a first conductivity type well region providedin a semiconductor substrate, or a first conductivity type semiconductorfilm disposed on an insulator; a gate insulating film formed on thefirst conductivity type semiconductor substrate, the first conductivitytype well region provided in the semiconductor substrate, or the firstconductivity type semiconductor film disposed on the insulator; a singlegate electrode formed on the gate insulating film; two charge holdingportions formed on sides of side walls of the single gate electrode; achannel region disposed under the single gate electrode; and secondconductivity type diffusion layer regions disposed on both sides of thechannel region, wherein the charge holding portions are structured so asto change a current amount flowing between one of the secondconductivity type diffusion layer regions and the other of the secondconductivity type diffusion layer regions when voltage is applied to thegate electrode by an amount of electric charges stored in the chargeholding portions, a reference voltage is applied to the other of thesecond conductivity type diffusion layer regions, a first voltage isapplied to the one of the second conductivity type diffusion layerregions, a second voltage is applied to the gate electrode such thatcarriers are injected into the the charge holding portion existing onthe side of the one of the second conductivity type diffusion layerregions, the second conductivity type diffusion layer regions arerespectively offset relative to edges of the single gate electrode, noelectrode exists on each of the two charge holding portions, and the twocharge holding portions are respectively located above part of thechannel region and part of each of the second conductivity typediffusion layer regions.
 2. The semiconductor storage device as definedin claim 1, wherein a third voltage is applied to the first conductivitytype semiconductor substrate, the first conductivity type well regionprovided in the semiconductor substrate, or the first conductivity typesemiconductor film disposed on the insulator.
 3. The semiconductorstorage device as defined in claim 1, wherein the first conductivitytype is P type, the second conductivity type is N type, the carriers arepositive holes, the first voltage is higher than the reference voltage,and the second voltage is lower than the reference voltage.
 4. Thesemiconductor storage device as defined in claim 1, wherein the firstconductivity type is N type, the second conductivity type is P type, thecarriers are electrons, the first voltage is lower than the referencevoltage, and the second voltage is higher than the reference voltage. 5.The semiconductor storage device as defined in claim 1, wherein thesecond conductivity type diffusion layer regions have an offsetstructure without an overlap region overlapping the gate electrode withinterposition of the gate insulating film.
 6. The semiconductor storagedevice as defined in claim 2, wherein an absolute value of voltagedifference between the second voltage and the third voltage is 0.7V ormore and 1V or less.
 7. The semiconductor storage device as defined inclaim 2, wherein a gate length of the gate electrode is 0.015 μm or moreand 0.5 μm or less.
 8. The semiconductor storage device as defined inclaim 1, wherein the charge holding portion is composed of a firstinsulator, a second insulator, and a third insulator, the charge holdingportion has a structure in which a film composed of the first insulatorhaving a function of storing electric charges is interposed between thesecond insulator and the third insulator, the first insulator is siliconnitride, the second and third insulators are silicon oxide.
 9. Thesemiconductor storage device as defined in claim 8, wherein a thicknessof the film composed of the second insulator on the channel region issmaller than a thickness of the gate insulating film and is 0.8 nm ormore.
 10. The semiconductor storage device as defined in claim 8,wherein a thickness of the film composed of the second insulator on thechannel region is larger than a thickness of the gate insulating filmand is 20 nm or less.
 11. The semiconductor storage device as defined inclaim 8, wherein the film composed of the first insulator having afunction of storing electric charges includes a portion having a surfacethat is approximately parallel to a surface of the gate insulating film.12. The semiconductor storage device as defined in claim 11, wherein thefilm composed of the first insulator having a function of storingelectric charges includes a portion extending in direction approximatelyparallel to a lateral side of the gate electrode.
 13. The semiconductorstorage device as defined in claim 1, wherein at least part of thecharge holding portion is formed so as to overlap part of the secondconductivity type diffusion layer region.
 14. The semiconductor storagedevice as defined in claim 2, wherein the first conductivity type is Ptype, the second conductivity type is N type, the carriers are positiveholes, the first voltage is higher than the reference voltage, thesecond voltage is lower than the reference voltage, and the thirdvoltage is higher than the reference voltage.
 15. The semiconductorstorage device as defined in claim 2, wherein the first conductivitytype is N type, the second conductivity type is P type, the carriers areelectrons, the first voltage is lower than the reference voltage, thesecond voltage is higher than the reference voltage, and the thirdvoltage is lower than the reference voltage.
 16. The semiconductorstorage device as defined in claim 15, wherein an absolute value ofvoltage difference between the second voltage and the third voltage is0.7V or more and 1V or less.
 17. A semiconductor storage devicecomprising: a first conductivity type semiconductor substrate, a firstconductivity type well region provided in a semiconductor substrate, ora first conductivity semiconductor film disposed on an insulator; a gateinsulating film formed on the first conductivity type semiconductorsubstrate, the first conductivity well region provided in thesemiconductor substrate, or the first conductivity type semiconductorfilm disposed on the insulator; a single gate electrode formed on thegate insulating film; two charge holding portions formed on sides ofside walls of the single gate electrode; a channel region disposed underthe single gate electrode; and second conductivity type diffusion layerregions disposed on both sides of the channel region, wherein the chargeholding portions are structured so as to change a current amount flowingbetween one of the second conductivity type diffusion layer regions andthe other of the second conductivity type diffusion layer regions whenvoltage is applied to the gate electrode by an amount of electriccharges stored in the charge holding portions, a reference voltage isapplied to the other of the second conductivity type diffusion layerregions, a first voltage is applied to the one of the secondconductivity type diffusion layer regions, a second voltage is appliedto the gate electrode such that carriers are injected into the chargeholding portion existing on the side of the one of the secondconductivity type diffusion layer regions, a third voltage is applied tothe first conductivity type semiconductor substrate, the firstconductivity type well region provided in the semiconductor substrate,of the first conductivity type semiconductor film disposed on theinsulator, the first conductivity type is P type, the secondconductivity type is N type, the carriers are positive holes, the firstvoltage is higher than the reference voltage, the second voltage islower than the reference voltage, and the third voltage is higher thanthe reference voltage.
 18. A semiconductor storage device comprising: afirst conductivity type semiconductor substrate, a first conductivitytype well region provided in a semiconductor substrate, or a firstconductivity type semiconductor film disposed on an insulator; a gateinsulating film formed on the first conductivity type semiconductorsubstrate, the first conductivity type well region provided in thesemiconductor substrate, or the first conductivity type semiconductorfilm disposed on the insulator; a single gate electrode formed on thegate insulating film; two charge holding portions formed on sides ofside walls of the single gate electrode; a channel region disposed underthe single gate electrode; and second conductivity type diffusion layerregions disposed on both sides of the channel region, wherein the chargeholding portions are structured so as to change a current amount flowingbetween one of the second conductivity type diffusion layer regions andthe other of the second conductivity type diffusion layer regions whenvoltage is applied to the gate electrode by an amount of electriccharges stored in the charge holding portions, wherein a referencevoltage is applied to the other of the second conductivity typediffusion layer regions, a first voltage is applied to the one of thesecond conductivity type diffusion layer regions, a second voltage isapplied to the gate electrode such that carriers are injected into thecharge holding portion existing on the side of the one of the secondconductivity type diffusion layer regions, a third voltage is applied tothe first conductivity type semiconductor substrate, the firstconductivity type well region provided in the semiconductor substrate,or the first conductivity type semiconductor film disposed on theinsulator, the first conductivity type is N type, the secondconductivity type is P type, the carriers are electrons, the firstvoltage is lower than the reference voltage, the second voltage ishigher than the reference voltage, and the third voltage is lower thanthe reference voltage.